1. Field of the Invention
The invention relates to an integrated circuit comprising a clock-signal generator and an associated clock-signal generating method. The invention is particularly valuable for integrated circuits used in contactless applications, such as smart cards, transponders etc.
In contactless circuits, the data and the energy received by the chip are transmitted by a reader (or sender) in the form of an amplitude-modulated radiofrequency signal or RF signal. The term “modulation” is the one most frequently used when referring to communications from the reader to the contactless circuit. As a complement, the contactless circuit may send digital data to the reader. In this case, the term used is “reverse modulation”.
2. Description of the Prior Art
One integrated circuit known for contactless applications comprises especially (FIG. 1) an antenna 11, a rectifier bridge 12, a voltage regulator 13, a logic circuit 14, a clock-signal generator 15 and the modulation/demodulation circuit 16.
The RF signal is received by the antenna 11 which produces two signals AC0 (shown in FIG. 2), AC1 having the form of two positive half waves, the RF signal being approximately equal to the result of the subtraction of the signal AC1 from the signal AC0.
The rectifier bridge 12 is a four-diode bridge. It has two inputs connected to two inputs/outputs of the antenna 11 to receive the two signals AC0, AC1, and one output at which a rectified voltage HVR is received. The voltage HVR is approximately the sum of two signals AC0, AC1; the mean amplitude of the rectified voltage varies directly as a function of the distance between the reader and the contactless integrated circuit. The mean amplitude of the rectified voltage may thus vary from approximately 2 V when the circuit is at some tens of centimeters from the reader to about 15-20 V when the circuit is at some millimeters from the reader. In practice, the voltage HVR is most usually limited to about 8 V by an appropriate device.
The voltage regulator 13 receives the rectified voltage HVR and produces a power supply voltage VDD having a nominal stable and continuous value VDD0 of about 3 V (for a 0.6 μm technology). This voltage will be used thereafter for the power supply of all the components of the integrated circuit. The regulator 13 comprises, inter alia, a filter comprising especially a set of resistors and capacitors associated according to known schemes.
The voltage VDD varies as follows. At the beginning of the reception of the RF signal sent out by the reader, during the transitional phase, the voltage VDD varies rapidly between a zero value and a nominal value VDD0. The voltage VDD then keeps its nominal value VDD0 until the interruption of the reception of the RF signal, either because the circuit stops sending or because the contactless circuit becomes located at far too great a distance from the reader, making any detection impossible at the antenna. In other words, after the transitional phase, the voltage VDD keeps the nominal value only if the energy received by the circuit by means of the RF signal is sufficient.
The modulation and demodulation circuit 16 may extract digital data, contained in the received RF signal, from the rectified voltage HVR. This digital data will be exploited by other components of the integrated circuit. For the reverse modulation (communication from the contactless circuit to the reader) the circuit 16 may also modulate data to be transmitted to the reader on the RF signal received and the RF signal modulated by the circuit 16 is then re-transmitted by means of the antenna 11.
The clock-signal generator 15 produces a clock signal CLK from the half-wave AC0 signal. The clock signal CLK is then used to set the rate of the operation of all the components of the integrated circuit.
Finally, the logic circuit 14 receives the power supply voltage VDD and produces different control signals when the power supply voltage VDD reaches a minimum value close to its nominal value VDD0. The control signals are, for example, the signals POR, CLKDIS, used to activate the circuit and of the clock-signal generator 15.
The clock-signal generator 15 is made conventionally by means of a set of logic gates. According to one embodiment, the clock-signal generator comprises a NOR type two-input logic gate to which there are respectively applied the signal AC0 and the control signal CLKDIS, and an output at which the clock signal CLK is produced.
The signal CLK varies in normal operation according to the timing diagram of FIG. 2. When the signal CLKDIS, herein equal to “0”, is active, the signal CLK is equal to “0” if the amplitude of the signal AC0 is greater than a threshold voltage VTRIG, and the signal CLK is equal to “1” if the amplitude of the signal AC0 is lower than the threshold voltage VTRIG. When the signal CLKDIS is inactive (in practice for a few microseconds after the start of reception of the RF signal), the signal CLK is equal to zero.
The threshold voltage VTRIG corresponds to a tripping threshold voltage of the logic converters used to make the NOR gate. The voltage VTRIG depends especially on the threshold voltage of the transistors constituting the inverters and especially the voltage VDD that powers them.
As can clearly be seen in FIG. 2, the signal CLK obtained has a cyclical ratio different from ½. This may raise difficulties of operation for certain components of the contactless circuit.
Another drawback of known clock-signal generators is that they are liable to work badly if the power supply voltage VDD undergoes major changes. This is for example the case when a reverse modulation starts.
Indeed, to transmit data to the reader, the circuit 16 modulates the RF signal with the data to be transmitted. The modulated signal is then re-transmitted to the reader by means of the antenna 11, as seen here above.
In practice, the RF signal is modulated by varying the load perceived by the antenna 11. This can be done by varying the load at output of the rectifier bridge 12, or again by drawing one and/or the other of the potentials AC0, AC1 to the ground.
This leads to a substantial and immediate drop in the amplitude of the AC0, AC1 as soon as the reverse modulation starts (the instant T0 in the timing diagram of FIG. 3). The reduction of the amplitude of the signal AC0 will lead to a reduction of the voltage VDD. The variations in voltage VDD are nevertheless far slower than those of the amplitude of the signal AC0; this is due essentially to the presence of filters in the voltage regulator 13. The voltage VDD will thus drop slightly during a few periods of the signal AC0, until it reaches a new value VDD1 that is far lower than VDD0. It will then keep this new value VDD1 throughout the duration of the reverse modulation. In the example of FIG. 3, three periods are needed for the voltage VDD to reach its stable value VDD1. In practice, about ten periods may be necessary.
The voltage VTRIG, which depends directly on the voltage VDD and conditions the generation of the clock signal CLK, will follow the variations of the voltage VDD (see FIG. 3). At the instant T1, the voltage VTRIG is still far higher than the amplitude of the signal AC0, so that the logic gates of the clock-signal generator do not trip: the signal CLK does not vary at the instant T1 whereas it should have varied. The same phenomenon recurs at the instant T2 of FIG. 3, inasmuch as the voltage VTRIG is still far too high as compared with the value of AC0. It is necessary to wait for a few half-wave periods AC0 to see a pulse appear on the signal (the instant T3 in the example of FIG. 3).
Thus, when the reverse modulation starts, the known clock-signal generators do not work accurately owing to the difference in behavior between the power supply voltage VDD and the amplitude of the half wave AC0.
This malfunction may have major consequences: in particular, it may give rise to errors of reception by the reader of the signal re-transmitted by the contactless circuit.
It is an object of the invention to make a new clock-signal generator that does not have such malfunctioning during major and rapid variations in the amplitude of the two half-waves AC0, AC1 on the antenna, for example when a reverse modulation is started.
It is another object of the invention to make a new clock-signal generator that produces perfectly even clock signals, with a cyclical ratio equal to ½.